Method for driving serdes circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHwang Ho CHOI, Jongshin SHIN, Seung-Hee YANG, Chang-Kyung SEONG
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Abstract
Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.
Claims20
A circuit driving method comprising:
- generating, via a common phase locked loop (PLL), a common clock signal to supply to a serializer/deserializer (SERDES) circuit;
- distributing the common clock signal to an eye opening monitor and a data transmission lane of the SERDES circuit;
- and
- driving the eye opening monitor and the data transmission lane using the common clock signal.
A circuit driving method comprising:
- generating, via a common phase locked loop (PLL), a first clock signal to supply to a serializer/deserializer (SERDES) circuit;
- generating, via a phase interpolator (PI) and a sigma-delta modulator (SDM) associated with the common PLL, a second clock signal having a higher clock phase shifting resolution than the first clock signal by shifting a phase of the first clock signal;
- and
- driving an eye opening monitor associated with the SERDES circuit using the second clock signal.
A method of driving a circuit, the method comprising:
- generating, via a phase locked loop (PLL) circuit, a common clock signal based on a reference clock signal;
- and
- transmitting the common clock signal from the PLL circuit to an eye opening monitor and a data transmission lane of the circuit, the eye opening monitor configured to detect a height and a width of an eye diagram of a signal.
Dependencies are inferred from the claim text.