Passive analog sample and hold in analog-to-digital converters

An analog to digital converter (ADC) facilitating passive analog sample and hold, comprising:

• a pair of binary weighted conversion capacitor arrays;
• a pair of sampling capacitors, wherein a sampling capacitance (Cs) of the sampling capacitors is a multiple of a conversion capacitance (Cd) of the conversion capacitors (Cs=N×Cd);
• integral nonlinearity (INL) compensation capacitors coupled to the sampling capacitors, wherein a ratio of a capacitance (Cpd) of the INL compensation capacitors to a parasitic capacitance (Cps) of the conversion capacitors is equal to the multiplier associated with the sampling capacitance (Cs) and the conversion capacitance (Cd) (Cpd=N×Cps);
• and
• a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase,
• wherein, during the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage,
• wherein, during the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage, and
• wherein, during the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.