Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit

A delay locked loop circuit comprising:

• a delay circuit including a plurality of serially connected delay buffers, each delay buffer including two or more serially connected delay units, each of the delay unit being capable of variably controlling each delay amount, the delay circuit configured to propagate an input clock and output a propagation clock;
• a phase comparator configured to compare phases of the propagation clock and the input clock;
• a charge pump configured to generate a charge current or a discharge current according to a phase difference, output from the phase comparator, between the propagation clock and the input clock;
• a capacitor configured to be charged by the charge current and discharged by the discharge current;
• a variable control voltage wiring configured to supply a voltage of the capacitor to a first delay unit included in each of the plurality of delay buffers, as a variable control voltage for controlling a delay amount of the first delay unit;
• and
• a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling a delay amount of the second delay unit.