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US 2016/0105188 A1Published application
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsJONG-PIL CHO, YOUNG-JOO LEE
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Abstract
A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.
Claims20
A semiconductor device comprising:
- an antenna that receives a first clock from a reader;
- a phase locked loop (PLL) that receives the received first clock and provides m candidate clocks having different phases derived from the first clock, where ‘m’ is a natural number;
- a phase difference detector that receives the first clock and a selected clock selected from among the m candidate clocks, and detect a phase difference between the first clock and the selected clock;
- a phase difference controller that receives the detected phase difference from the phase difference detector and selects another selected clock from among the m candidate clocks;
- and
- a driver that receives the another selected clock from the phase difference controller and transmission data to be output to the reader, and provides the transmission data synchronously with the another selected clock to the reader.
3 more elements
A semiconductor device comprising:
- an antenna that receives a first clock from a reader;
- a phase locked loop (PLL) that receives the first clock and outputs a second clock having a predetermined phase difference with the first clock;
- a driver that receives the second clock output and transmission data to be output to the reader, and outputs the transmission data to the reader synchronously with the second clock;
- and
- an output controller that varies a magnitude of an output signal of the driver.
2 more elements
A semiconductor device comprising:
- an antenna configured that receives a first clock from a reader;
- a phase locked loop (PLL) that receives the first clock and provides a second clock having a predetermined phase difference with the first clock;
- a driver that receives the second clock and transmission data to be output to the reader, and outputs the transmission data to the reader synchronously with the second clock;
- and
- a duty ratio controller that varies a duty ratio of the transmission data synchronously provided to the driver.
2 more elements
Dependencies are inferred from the claim text.