Fll oscillator/clock with an fll control loop including a switched capacitor resistive divider

An FLL (frequency locked loop) oscillator circuit suitable for use as a clock generator, comprising

• a frequency locked loop (FLL) oscillator generating an oscillator signal FLL_clk with a frequency fOSC based on an oscillator control signal;
• an FLL control loop configured to generate the oscillator control signal based on the frequency of the FLL_clk output of the FLL oscillator, including
• a switched-capacitor resistor-divider circuit configured to provide a frequency control signal based on the frequency of the FLL_clk;
• a spread spectrum clocking (SSC) generator configured to generate a spread spectrum control signal corresponding to a spread spectrum modulation function;
• and
• an FLL control circuit configured to provide the oscillator control signal based on an FLL control signal, and including:
• an amplifier circuit receiving the spread spectrum control signal from the SSC generator at a noninverting input, and the frequency control signal from the switched-capacitor resistor-divider at an inverting input, and outputting the FLL control signal corresponding to the frequency control signal with spread spectrum modulation;
• the FLL control circuit providing the oscillator control signal with spread spectrum modulation based on the FLL control signal;
• such that the FLL oscillator generates the FLL_clk with spread spectrum modulation;
• the switched-capacitor resistor-divider circuit, including:
• a resistor coupled at an R-divider node to a switched capacitor;
• the switched capacitor configured to convert the frequency fOSC of FLL_clk to a resistance;
• such that the resistor and the switched capacitor operate as resistor divider that outputs the frequency control signal at the R-divider node.

A method of generating a clock using an FLL (frequency locked loop) oscillator circuit, comprising

• generating an oscillator signal FLL_clk with a frequency fOSC based on an oscillator control signal;
• generating the oscillator control signal based on a frequency control signal representative of the frequency of the FLL_clk output of the FLL oscillator;
• generating the frequency control signal based on the frequency of the FLL_clk, using a switched-capacitor resistor-divider that includes a resistor and a switched capacitor coupled at an R-divider node by:
• switching the switching capacitor in response the FLL_clk to convert the frequency fosc to a switched-cap resistance;
• outputting the frequency control signal from the R-divider node based on voltage division provided by the resistor and the switched-cap resistance.