Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof

An integrated circuit comprising:

• a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, during operation, is configurable to connect with at least one logic tile that is adjacent to an edge, wherein a first logic tile of the plurality of logic tiles includes:
• at least one input clock path which is associated with an edge of the logic tile, wherein the input clock path is configurable to receive a tile input clock signal;
• a plurality of output clock paths, including:
• a first output clock path which is associated with a first edge of the first logic tile, wherein the first output clock path includes a first u-turn circuit to output a first tile clock signal having a predetermined skew relative to the tile input clock signal;
• a second output clock path which is associated with a second edge of the first logic tile, wherein the second output clock path includes a second u-turn circuit to output a second tile clock signal having a predetermined skew relative to a first output clock signal;
• tile clock generation circuitry, coupled to one or more of the plurality of output clock paths, to generate at least one tile clock using the second tile clock signal;
• and
• programmable logic circuitry to perform operations using the at least one tile clock.

An integrated circuit comprising:

• a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, during operation, is configurable to connect with at least one logic tile that is adjacent to an edge, and wherein a first logic tile of the plurality of logic tiles includes:
• a plurality of input clock paths, each input clock path is associated with an edge of the logic tile, wherein:
• a first input clock path is configurable to receive a first tile input clock signal, and
• a second input clock path is configurable to receive a second tile input clock signal;
• a plurality of output clock paths, wherein each output clock path is associated with an edge of the first logic tile, wherein:
• a first output clock path, which is associated with a first edge of the first logic tile, includes at least one u-turn circuit to (i) receive a signal having a first predetermined skew relative to the first tile input clock signal and (ii) output a first tile clock signal having a second predetermined skew relative to the first tile input clock signal, and
• a second output clock path, which is associated with a second edge of the first logic tile, includes at least one u-turn circuit to (i) receive a signal having a first predetermined skew relative to the second tile input clock signal and (ii) output a second tile clock signal having a second predetermined skew relative to the second tile input clock signal;
• first tile clock generation circuitry, coupled to one or more of the plurality of output clock paths, to generate a first tile clock using the first tile clock signal;
• and
• programmable logic circuitry, coupled to the first clock generation path, to perform operations using the first tile clock.