Receiver circuit and signal receiving method thereof

A receiver circuit, comprising:

• a first restriction circuit configured to provide an input signal higher than a first reference voltage to a first node;
• a second restriction circuit configured to provide the input signal lower than a second reference voltage to a second node;
• a first PMOS transistor configured to pull up an output node based on a voltage of the first node;
• a first NMOS transistor configured to pull down the output node based on a voltage of the second node;
• a second PMOS transistor having a gate connected to the first node, and being connected between a power supply voltage and a source of the first PMOS transistor;
• a first hysteresis setting part configured to control a voltage of the source of the first PMOS transistor based on the output signal;
• a second NMOS transistor having a gate connected to the second node, and being connected between a source of the first NMOS transistor and a ground;
• and
• a second hysteresis setting part configured to control a voltage of the source of the first NMOS transistor based on the output signal.