Clock buffers with pulse drive capability for power efficiency

A clock driver for an integrated circuit, comprising

• a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output, the input for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal for the integrated circuit, the output connected to the positive pulse driving branch and the negative pulse driving branch;
• and
• a pulse generator having a positive pulse generator portion that is connected to an output of the positive pulse driving branch of the multi-stage delay cell and a negative pulse generator portion that is connected to an output of the negative pulse driving branch of the multi-stage delay cell,
• wherein the pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.