Low power externally biased power-on-reset circuit

A power-on-reset circuit for generating a power-on-reset signal upon detecting that a supply voltage has reached a desired level comprising:

• a sense circuit comprising:
• (i) an inverter powered by a known bias voltage;
• (ii) a feedback circuit powered by the supply voltage;
• and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level;
• and
• a delayed buffer coupled to the output node of the sense circuit that generates the power-on-reset signal in response to the voltage transition;
• wherein the feedback circuit shuts off the sense circuit in response to the voltage transition;
• wherein the power-on-reset circuit generates the power-on-reset signal for a local system;
• and
• wherein the known bias voltage is provided by an external system, the delayed buffer comprising:
• a first sub-inverter that is input coupled to the output node of the sense circuit, and output coupled to a capacitive delay node;
• a second sub-inverter that is input coupled to the capacitive delay node, and output coupled to a second sub-inverter output node;
• a first transistor that is gate coupled to the inverter output node, and source coupled to the known bias voltage;
• a second transistor that is gate coupled to the second sub-inverter output node and drain coupled to the capacitive delay node;
• and
• a capacitive delay element coupled to the capacitive delay node;
• wherein a drain of the first transistor is coupled to a source of the second transistor;
• and
• wherein a delay period of the delayed buffer is set by the capacitive delay element.

A power-on-reset circuit:

• an inverter that is powered by an external power source and that outputs a signal when a supply voltage exceeds the external power source;
• a delayed buffer that is operatively coupled to an inverter output node of the inverter to receive the signal from the inverter;
• a feedback circuit;
• and
• a voltage divider coupled to the supply voltage, an inverter input node of the inverter, and the feedback circuit;
• wherein the feedback circuit isolates the voltage divider from ground and couples the voltage divider to the supply voltage in response to the signal;
• and
• wherein the delayed buffer generates a power-on-reset signal in response to the signal, the voltage divider further comprising:
• a first transistor that is gate coupled to the inverter input node, and that provides a first source-drain path between the supply voltage and the inverter input node;
• and
• a second transistor that is gate coupled to the inverter input node, and that provides a second source-drain path along a circuit branch between the input of the inverter and a ground node.

A power-on-reset circuit:

• an inverter that is powered by an external power source and that outputs a signal when a supply voltage exceeds the external power source;
• a delayed buffer that is operatively coupled to an inverter output node of the inverter to receive the signal from the inverter;
• a feedback circuit;
• and
• a voltage divider coupled to the supply voltage, an inverter input node of the inverter, and the feedback circuit;
• wherein the feedback circuit isolates the voltage divider from ground and couples the voltage divider to the supply voltage in response to the signal;
• and
• wherein the delayed buffer generates a power-on-reset signal in response to the signal, the voltage divider further comprising:
• a first resistor coupled between the external power source and the inverter input node;
• and a second resistor forming a conductive path on a circuit branch between the inverter input node and a ground node, the feedback circuit comprising:
• a first transistor that is gate coupled to the inverter output node and that provides a first source-drain path between the supply voltage and the inverter input node;
• and
• a second transistor that is gate coupled to the inverter output node and that provides a second source-drain path along the circuit branch between the second resistor and the ground node.

A power-on-reset circuit:

• an inverter that is powered by an external power source and that outputs a signal when a supply voltage exceeds the external power source;
• a delayed buffer that is operatively coupled to an inverter output node of the inverter to receive the signal from the inverter;
• a feedback circuit;
• and
• a voltage divider coupled to the supply voltage, an inverter input node of the inverter, and the feedback circuit;
• wherein the feedback circuit isolates the voltage divider from ground and couples the voltage divider to the supply voltage in response to the signal;
• and
• wherein the delayed buffer generates a power-on-reset signal in response to the signal, the delayed buffer comprising:
• a first sub-inverter that is input coupled to the inverter output node and output coupled to a capacitive delay node;
• a second sub-inverter that is input coupled to the capacitive delay node, and output coupled to a second sub-inverter output node;
• a first transistor that is gate coupled to the inverter output node, and source coupled to the external power source;
• a second transistor that is gate coupled to the second sub-inverter output node and drain coupled to the capacitive delay node;
• and
• a capacitive delay element coupled to the capacitive delay node;
• wherein a drain of the first transistor is coupled to a source of the second transistor;
• and
• wherein a delay period of the delayed buffer is set by the capacitive delay element.

A power-on-reset circuit comprising:

• an inverter coupled between a known bias voltage and a ground node;
• a first transistor that is coupled between a supply voltage and an input node of the inverter and that has a first control electrode coupled to the input node of the inverter;
• a second transistor that forms a portion of a circuit branch between the first transistor and the ground node and that has a second control electrode coupled to the input node of the inverter;
• a delayed buffer that receives a transition signal from the inverter when the supply voltage exceeds the known bias voltage;
• and
• a feedback circuit that shorts the circuit branch and pulls the input node of the inverter to the supply voltage in response to the transition signal, the feedback circuit further comprising:
• a third transistor that is gate coupled to an output node of the inverter and that forms a first source-drain path between the supply voltage and the input node of the inverter;
• a fourth transistor that is gate coupled to the output node of the inverter and that forms a second source-drain path between the second transistor and the ground node along the circuit branch.

A power-on-reset circuit comprising:

• an inverter coupled between a known bias voltage and a ground node;
• a first transistor that is coupled between a supply voltage and an input node of the inverter and that has a first control electrode coupled to the input node of the inverter;
• a second transistor that forms a portion of a circuit branch between the first transistor and the ground node and that has a second control electrode coupled to the input node of the inverter;
• a delayed buffer that receives a transition signal from the inverter when the supply voltage exceeds the known bias voltage;
• and
• a feedback circuit that shorts the circuit branch and pulls the input node of the inverter to the supply voltage in response to the transition signal, the delayed buffer comprising:
• a delayed buffer input node coupled to the output node of the inverter;
• a first sub-inverter that has a first sub-inverter input coupled to the delayed buffer input node and a first sub-inverter output coupled to a delay node;
• a second sub-inverter that has a second sub-inverter input coupled to the delay node;
• and
• a delay element coupled between the delay node and the ground node that sets the delay of the delayed buffer.

A power-on-reset circuit comprising:

• an inverter coupled between a known bias voltage and a ground node;
• a first transistor that is coupled between a supply voltage and an input node of the inverter and that has a first control electrode coupled to the input node of the inverter;
• a second transistor that forms a portion of a circuit branch between the first transistor and the ground node and that has a second control electrode coupled to the input node of the inverter;
• a delayed buffer that receives a transition signal from the inverter when the supply voltage exceeds the known bias voltage;
• and
• a feedback circuit that shorts the circuit branch and pulls the input node of the inverter to the supply voltage in response to the transition signal, the feedback circuit further comprising:
• a third transistor that is gate coupled to the delay node and that forms a first source-drain path between the supply voltage and the input node of the inverter;
• a fourth transistor that is gate coupled to the delay node and that forms a second source-drain path between the second transistor and the ground node along the circuit branch.