Duty cycle error detection device and duty cycle correction device having the same

A duty cycle correction device, comprising:

• a duty cycle error detection device configured to generate a sign signal, which represents a longer period between a high level period of a clock signal and a low level period of the clock signal, and a duty error digital code, which corresponds to a difference between a length of the high level period of the clock signal and a length of the low level period of the clock signal;
• a phase align circuit configured to output one of the clock signal and an inverted clock signal, which corresponds to an inverted version of the clock signal, as a first internal clock signal based on a logic level of the sign signal, and to generate a second internal clock signal by delaying the other one of the clock signal and the inverted clock signal for a time corresponding to a half of the duty error digital code;
• and
• a clock synthesis circuit configured to generate a corrected clock signal, which toggles at each rising edge of the first internal clock signal and each rising edge of the second internal clock signal.

An electronic device, comprising:

• a clock generator configured to generate a clock signal;
• a duty cycle correction device configured to correct a duty cycle error of the clock signal to generate a corrected clock signal;
• a memory device configured to operate in synchronization with the corrected clock signal;
• and
• a processor configured to write data in the memory device and to read the data from the memory device,
• wherein the duty cycle correction device includes,
• a duty cycle error detection device configured to generate a sign signal, which represents a longer period between a high level period of the clock signal and a low level period of the clock signal, and a duty error digital code, which corresponds to a difference between a length of the high level period of the clock signal and a length of the low level period of the clock signal;
• a phase align circuit configured to output one of the clock signal and an inverted clock signal, which corresponds to an inverted version of the clock signal, as a first internal clock signal based on a logic level of the sign signal, and to generate a second internal clock signal by delaying the other one of the clock signal and the inverted clock signal for a time corresponding to a half of the duty error digital code;
• and
• a clock synthesis circuit configured to generate a corrected clock signal, which toggles at each rising edge of the first internal clock signal and each rising edge of the second internal clock signal.