Resistive random access memory device having nano-scale tip and nanowire, memory array using the same and fabrication method thereof

A memory array comprising:

• a semiconductor substrate;
• a plurality of bit lines formed in a first direction on the semiconductor substrate;
• and
• a plurality of word lines formed in a second direction across the bit lines, a resistance change layer being located between the word lines and the bit lines,
• wherein each of the bit lines is formed of a semiconductor line doped with an impurity, the semiconductor line having upwardly protruding tapered tip structures, and
• wherein each of the word lines is formed of a nanowire passing over the tip structures of the bit lines along the second direction.

A method for fabricating a memory array, comprising:

• a first step of protruding a plurality of semiconductor lines for forming a plurality of contacts and bit lines by etching a semiconductor substrate;
• a second step of forming an isolation insulating film by depositing a first insulating material on the semiconductor substrate and etching the first insulating material to expose upper parts of the semiconductor lines and to be insulated from each other;
• a third step of forming protruding patterns on the upper parts of the semiconductor lines;
• a fourth step of forming upwardly protruding tapered tip structures from the protruding patterns;
• a fifth step of forming a plurality of contacts and bit lines on the upper parts of the semiconductor lines by an ion implantation process;
• a sixth step of forming a resistance change layer on the upper parts of the tip structures of the each bit line by depositing a resistance change material, and forming a plurality of contact holes that reach the each contact;
• and
• a seventh step of forming a plurality of word lines with nanowires and forming a plurality of word line contacts and a plurality of bit line contacts filled in the contact holes on the resistance change layer.