Resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof

A memory array comprising:

• a semiconductor substrate;
• a plurality of bit lines formed in a first direction on the semiconductor substrate;
• and
• a plurality of word lines formed in a second direction across the bit lines, a resistance change layer being located between the word lines and the bit lines,
• wherein the bit lines are formed in one body with the semiconductor substrate, each of the bit lines being a bottom electrode line doped with an impurity and electrically insulated from adjacent lines with an isolation insulating film, the bottom electrode line having upwardly protruding tapered tip structures along the first direction,
• wherein an interlayer insulating film is further formed between the bit lines and the resistance change layer, the interlayer insulating film wrapping around the tip structures except for upper parts of the tip structures,
• wherein the resistance change layer is formed on the upper parts of the tip structures of the each bit line, the interlayer insulating film and the isolation insulating film, and
• wherein each of the word lines is formed of a top electrode line passing over the tip structures of the bit lines along the second direction.

A method for fabricating a memory array, comprising:

• a first step of protruding a plurality of semiconductor lines for forming a plurality of contacts and bit lines by etching a semiconductor substrate;
• a second step of forming an isolation insulating film by depositing a first insulating material on the semiconductor substrate and etching the first insulating material to expose upper parts of the semiconductor lines and to be insulated from each other;
• a third step of forming protruding patterns on the upper parts of the semiconductor lines;
• a fourth step of forming upwardly protruding tapered tip structures from the protruding patterns;
• a fifth step of forming a plurality of contacts and bit lines on the upper parts of the semiconductor lines by an ion implantation process;
• a sixth step of depositing a second insulating material on the upper parts of the plurality of contacts and bits lines and the isolation insulating film and etching the second insulating material and the isolation insulating film to form an interlayer insulating film with the second insulating material, the interlayer insulating film wrapping around the tip structures except for upper parts of the tip structures;
• a seventh step of forming a resistance change layer on the upper parts of the tip structures of the each bit line, the interlayer insulating film and the isolation insulating film by depositing a resistance change material, and forming a plurality of contact holes that reach the each contact;
• and
• an eighth step of forming a plurality of word lines and word line contacts and a plurality of bit line contacts filled in the contact holes by depositing and etching a conductive material on the resistance change layer.