Structure and Method for FinFET Device

A fin-like field-effect transistor (FinFET) device comprising:

• a fin structure disposed over a substrate, the fin structure including:
• semiconductor oxide layer disposed over the substrate, wherein the semiconductor oxide layer has a top surface facing away from the substrate;
• a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, wherein the first semiconductor material layer has a top surface facing away from the substrate and an opposing bottom surface facing the substrate;
• and
• a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer;
• a high-k/metal gate (HK/MG) disposed over the fin structure, wherein the HK/MG gate extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer;
• and
• a source/drain (S/D) feature adjacent to the fin-like structure, wherein the S/D features physically contacts:
• the dielectric sidewall spacer;
• and
• the first semiconductor material layer;
• a gate dielectric layer disposed over the fin structure, wherein the gate dielectric layer physically contacts the top surface and the bottom surface of the first semiconductor layer and physically contacts the top surface of the semiconductor oxide layer;
• and
• a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.

A fin-like field-effect transistor (FinFET) device comprising:

• a fin structure disposed over a substrate, the fin structure including:
• a semiconductor oxide layer disposed over the substrate;
• a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer;
• and
• a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer;
• a gate dielectric layer disposed over and physically contacting a top surface and a bottom surface of the first semiconductor layer;
• and
• a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.