Methods of Fabricating Semiconductor Devices

A method of fabricating a semiconductor device, the method comprising:

• forming an interlayer insulation layer on a substrate, the interlayer insulation layer covering a dummy silicon gate and a gate hard mask sequentially stacked;
• exposing the dummy silicon gate by removing the interlayer insulation layer and the gate hard mask on the dummy silicon gate;
• after removing the gate hard mask, recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of a recessed interlayer insulation layer;
• forming a pre-etch stop layer on the top surface of the recessed interlayer insulation layer and the portion of the dummy silicon gate protruding above the top surface of a recessed interlayer insulation layer;
• forming an etch stop layer exposing the dummy silicon gate on the recessed interlayer insulation layer by removing the pre-etch stop layer formed on a top surface of the dummy silicon gate using a chemical mechanical polishing (CMP) process;
• and
• forming a trench exposing the substrate by removing the dummy silicon gate after the forming of the etch stop layer.

A method of fabricating a semiconductor device, the method comprising:

• forming a plurality of first dummy gate structures each including a first dummy silicon gate on a first region on a substrate, wherein a distance between two adjacent ones of the first dummy gate structures is a first distance;
• forming a plurality of second dummy gate structures each including a second dummy silicon gate on a second region on the substrate, wherein a distance between two adjacent ones of the second dummy gate structures is a second distance greater than the first distance;
• forming an interlayer insulation layer on the substrate, the interlayer insulation layer surrounding the first dummy silicon gate and the second dummy silicon gate and exposing a top surface of the first dummy silicon gate and a top surface of the second dummy silicon gate;
• recessing a portion of the interlayer insulation layer such that the first dummy silicon gate and the second dummy silicon gate protrude above a top surface of the recessed interlayer insulation layer;
• forming a pre-etch stop layer on the top surface of the recessed interlayer insulation layer and the first and second dummy silicon gates, wherein a height ranging from a top surface of the substrate to a bottommost part of an upper surface of the pre-etch stop layer of the second region is greater than a height ranging from the top surface of the substrate to the top surface of the second dummy silicon gate;
• and
• removing the pre-etch stop layer on the first and second dummy silicon gates using a chemical mechanical polishing (CMP) process to form an etch stop layer on the recessed interlayer insulation layer,
• wherein a top surface of the etch stop layer in the first region and a top surface of the etch stop layer in the second region are coplanarly positioned.