Semiconductor device and method for fabricating the same

A semiconductor device comprising:

• a semiconductor substrate including first and second regions;
• a buffer layer formed on the semiconductor substrate, the buffer layer having a lattice constant different from that of the semiconductor substrate;
• a first channel layer formed on the buffer layer of the first region, the first channel layer having a lattice constant smaller than the lattice constant of the buffer layer;
• a second channel layer formed on the buffer layer of the second region, the second channel layer having a lattice constant greater than the lattice constant of the buffer layer;
• and
• a spacer layer disposed between the second channel layer and the buffer layer, the spacer layer having a lattice constant that gradually increases from a top surface of the buffer layer toward a bottom surface of the second channel layer,
• wherein top surfaces of the first and second channel layers are coplanar with each other, and
• a bottom surface of the spacer layer is disposed at substantially the same level as or a lower level than a bottom surface of the first channel layer.

A semiconductor device comprising:

• a semiconductor substrate including a first region and a second region;
• a first fin structure on the first region, the first fin structure including a first buffer pattern and a first channel pattern sequentially stacked;
• a second fin structure on the second region, the second fin structure including a second buffer pattern, a second channel pattern on the second buffer pattern, and a spacer pattern disposed between the second buffer pattern and the second channel pattern,
• a first metal-oxide-semiconductor (MOS) transistor provided on the first fin structure, a first gate electrode, and a first gate insulating layer between the first fin structure and the first gate electrode;
• and
• a second MOS transistor provided on the second fin structure, a second gate electrode, and a second gate insulating layer between the second fin structure and the second gate electrode,
• wherein the first and second buffer patterns include a first semiconductor material of which a lattice constant is different from that of the semiconductor substrate,
• wherein the first channel pattern includes a second semiconductor material of which a lattice constant is smaller than the lattice constant of the first semiconductor material,
• wherein the second channel pattern includes a third semiconductor material of which a lattice constant is greater than the lattice constant of the first semiconductor material, and
• wherein the spacer pattern has a lattice constant that gradually increases from the second buffer pattern toward the second channel pattern.

An electronic device, comprising:

• a semiconductor substrate having a first and a second regions;
• a buffer layer formed on the semiconductor substrate on the first region and on the second region;
• a first channel layer formed on the buffer layer on the first region;
• a second channel layer formed on the buffer layer on the second region;
• and
• a spacer layer formed between the buffer layer and the second channel layer,
• wherein the lattice constant of the spacer layer increases gradually from a region adjacent to the buffer layer to a region adjacent to the second channel layer.

A semiconductor device, comprising:

• a semiconductor substrate including a first region and a second region;
• a buffer layer on the first region and second region of the semiconductor substrate;
• a first channel pattern on the buffer layer of the first region;
• a providing a spacer pattern on the buffer layer of the second region;
• and
• a second channel pattern on the spacer pattern;
• wherein the lattice constant of the spacer pattern increases from a surface of the spacer pattern adjacent to the buffer layer to a surface of the spacer pattern adjacent to the second channel pattern.