Common contact of n++ and p++ transistor drain regions in cmos

An integrated circuit, comprising:

• a first transistor having a first conductivity type, the first transistor comprising a first gate, an first source region and a first drain region disposed on opposite sides of the first gate;
• a second transistor having a second conductivity type opposite from the first conductivity type of the first transistor, the second transistor comprising a second gate, a second source region and a second drain region disposed on opposite sides of the second gate, wherein the p-type drain region of the second transistor is abutted against the n-type drain region of the first transistor;
• and
• an output contact in electrical communication with the first drain region of the first transistor and the second drain region of the second transistor, wherein the first drain region of the first transistor and the second drain region of the second transistor each comprises a heavily doped region.

A method of forming an integrated circuit, comprising:

• forming a first transistor having a first conductivity type on a substrate, the first transistor comprising a first gate, an first source region and a first drain region disposed on opposite sides of the first gate;
• forming a second transistor having a second conductivity type opposite from the first conductivity type of the first transistor, the second transistor comprising a second gate, a second source region and a second drain region disposed on opposite sides of the second gate, wherein the second drain region of the second transistor is abutted against the first drain region of the first transistor;
• covering the second transistor and implanting dopants into the first drain region of the first transistor by tilting the substrate at an angle;
• activating implanted dopants in the first drain region, wherein the first drain region is heavily doped with dopants having the first conductivity type;
• covering the first transistor and implanting dopants into the second drain region of the second transistor by tilting the substrate at an angle;
• activating implanted dopants in the second drain region, wherein the second drain region is heavily doped with dopants having the second conductivity type;
• and
• forming an output contact layer over the first drain region of the first transistor and the second drain region of the second transistor, wherein the output contact is in electrical communication with the first drain region of the first transistor and the second drain region of the second transistor.