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US 2016/0104721 A1Published application
Vertical type memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsKwang-Soo SEOL, Seong-Soon CHO
Life of this patent
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Abstract
A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
Claims20
A semiconductor device, comprising:
- a selection line extending in a first direction;
- first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the same selection line;
- first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
- a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line;
- and
- a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line,
- wherein the first sub-interconnection has a first protrusion protruding in the first direction, and
- wherein the second sub-interconnection has a second protrusion protruding in a direction opposite to the first direction.
5 more elements
A semiconductor device, comprising:
- a selection line extending in a first direction;
- first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the same selection line;
- first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
- a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line;
- and
- a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line,
- wherein the first sub-interconnection has a protrusion protruding in the first direction, and
- wherein the second sub-interconnection has a substantially rectangular shape extending in the second direction in plan view.
5 more elements
Dependencies are inferred from the claim text.