Apparatuses and methods for forming multiple decks of memory cells
AssigneeMicron Technolgy, Inc.
InventorsZhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
Life of this patent
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Abstract
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
Claims24
An apparatus comprising:
- first memory cells located in different levels in a first portion of the apparatus;
- second memory cells located in different levels in a second portion of the apparatus;
- a switch located in one of the first and second portions and between the first and second memory cells;
- first control gates located in the first portion to access the first memory cells;
- second control gates located in the second portion to access the second memory cells;
- and
- a third control gate to control the switch during an operation of the apparatus, the third control gate located the between the first and second control gates.
-23. (canceled)
A method comprising:
- applying a first voltage to first control gates and second control gates of a memory device during one of an erase operation and an erase verify operation of the memory device;
- and
- applying a second voltage greater than the first voltage to an additional control gate of the memory device during one of the erase operation and the erase verify operation, the additional control gate being located between the first control gates and the second control gates.
A method comprising:
- applying a first voltage to first control gates and second control gates of a memory device during an operation of the memory device, each of the first and second control gates used to access memory cells associated with the first and second control gates;
- and
- applying a second voltage to an additional control gate of the memory device during the operation, the additional control gate being located between the first control gates and the second control gates, wherein the additional control gate is not configured to access a memory cell of the memory device.
Dependencies are inferred from the claim text.