Methods of forming integrated circuit devices

A method of forming an integrated circuit device, comprising:

• forming an isolated well structure in a first region of a semiconductor substrate;
• forming a first oxide in a second region of the semiconductor substrate, wherein the second region of the semiconductor substrate is recessed from the first region of the semiconductor substrate;
• forming a second oxide over the second region of the semiconductor substrate;
• forming polysilicon over the second oxide;
• forming a third oxide over the second region of the semiconductor substrate to be level with a surface of the first region of the semiconductor substrate;
• forming a fourth oxide over the first region of the semiconductor substrate and the second region of the semiconductor substrate;
• forming a charge trapping material over the fourth oxide over the first region of the semiconductor substrate and the second region of the semiconductor substrate;
• removing the charge trapping material, the fourth oxide and the third oxide over the second region of the semiconductor substrate;
• forming a dielectric over the charge trapping material;
• forming a metal over the dielectric and over the polysilicon;
• forming a first gate structure over the second region of the semiconductor substrate, the first gate structure comprising a portion of the metal, a portion of the polysilicon and a portion of the first oxide;
• forming a second gate structure over the second region of the semiconductor substrate, the second gate structure comprising a portion of the metal, a portion of the polysilicon and a portion of the second oxide;
• and
• forming a memory cell over the isolated well structure, the memory cell comprising a portion of the metal, a portion of the dielectric, a portion of the charge trapping material and a portion of the fourth oxide.

A method of forming an integrated circuit device, comprising:

• forming an isolated p-well structure in a first region of a semiconductor substrate;
• forming a second p-well in a second region of the semiconductor substrate, wherein the second region of the semiconductor substrate is recessed from the first region of the semiconductor substrate;
• selectively oxidizing a portion of a second region of the semiconductor substrate adjacent to the second p-well to form a first oxide;
• forming a second oxide over the second region of the semiconductor substrate;
• forming polysilicon over the second oxide;
• forming a third oxide over the second region of the semiconductor substrate to be level with the first region of the semiconductor substrate;
• forming a tunnel oxide over the first region of the semiconductor substrate and the second region of the semiconductor substrate;
• forming a charge trapping material over the tunnel oxide over the first region of the semiconductor substrate and the second region of the semiconductor substrate;
• removing the charge trapping material, the tunnel oxide and the third oxide over the second region of the semiconductor substrate;
• forming a dielectric over the charge trapping material;
• forming a metal over the dielectric and over the polysilicon concurrently;
• forming a first gate structure over the second region of the semiconductor substrate for operation at a first voltage level, the first gate structure comprising a portion of the metal, a portion of the polysilicon and a portion of the first oxide;
• forming a second gate structure over the second p-well for operation at a second voltage level lower than the first voltage level, the second gate structure comprising a portion of the metal, a portion of the polysilicon and a portion of the second oxide;
• and
• forming a memory cell over the isolated p-well structure, the memory cell comprising a portion of the metal, a portion of the dielectric, a portion of the charge trapping material and a portion of the tunnel oxide.