US 2016/0104714 A1Published application

Semiconductor integrated circuit and method of producing the same

AssigneeTohoku University

InventorsTetsuo Endoh, Seo Moon-Sik

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Abstract

Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.

Claims16

Dependent claims

A method of producing a semiconductor integrated circuit, comprising:

a step of layering three types of different layers on a substrate;
a step of forming an opening up to the surface of the substrate;
a step of etching a region functioning as a floating gate in the layers layered adjacent to the opening;
a step of depositing a semiconductor material in the opening including the region functioning as a floating gate;
a step of subjecting a region including the deposited semiconductor material to an anisotropic etching to form an opening in a region in which a semiconductor pillar and a tunnel insulating layer are to be formed and to form a floating gate;
a step of depositing a tunnel insulating layer on a side wall of the opening formed by the anisotropic etching;
a step of depositing a semiconductor material on the opening surrounded by the tunnel insulating layer to form a semiconductor pillar;
a step of etching the three types of different layers having etching selectivity to one another except for a layer including the floating gate and a layer functioning as a separation layer between cells;
a step of forming another insulating layer on the floating gate, the layer functioning as the separation layer, and the tunnel insulating layer;
a step of depositing, on the another insulating layer, a material to be used for a control gate;
and
a step of etching the material to be used for a control gate so as to form a control gate and a word line.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/880,690Filed 12 Oct 2015
Priority: JP 2010-11270514 May 2010
Published: 14 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/0425
Comprising cells containing floating gate transistors: comprising cells containing a merged floating gate and select transistor
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application13/697,905Division · filed 28 Jan 2013
Application14/600,554Division · filed 20 Jan 2015
Application14/880,690Division
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From the US filing history. Foreign family members aren’t listed.