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US 2016/0104711 A1Published application
Non-volatile memory
AssigneeeMemory Technology Inc.
InventorTe-Hsun Hsu
Life of this patent
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Abstract
A non-volatile memory including a substrate, a floating gate transistor, a select transistor and a stress-releasing transistor. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor.
Claims20
A non-volatile memory, comprising:
- a substrate;
- and
- a floating gate transistor, a select transistor and a stress-releasing transistor, disposed on the substrate and coupled in series with each other, wherein the stress-releasing transistor is located between the floating gate transistor and the select transistor.
Dependencies are inferred from the claim text.