Fin-like field effect transistor (finfet) device and method of manufacturing same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJeff J. Xu, Chih-Hao Chang
Life of this patent
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Abstract
A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
Claims20
A integrated circuit device comprising:
- a first fin and a second fin disposed over a semiconductor substrate;
- an isolation structure disposed between the first and second fins, such that the first and second fins are isolated from each other;
- a gate structure disposed over a portion of the first and second fins, the gate structure traversing the first and second fins, thereby separating a source region and a drain region of the first and second fins;
- a first semiconductor layer disposed over another portion of the first and second fins;
- and
- a second semiconductor layer disposed over the first semiconductor layer, wherein the source and drain regions of the first and second fins include a portion of the first and second semiconductor layers, wherein the second semiconductor layer is an epitaxial semiconductor layer.
A device comprising:
- a first fin and a second fin disposed over a semiconductor substrate, the first fin defining a first channel region and a first source/drain region and the second fin defining a second channel region and a second source/drain region;
- a gate structure disposed over the first channel region of the first fin and the second channel region of the second fin;
- a first semiconductor layer disposed directly on the first fin in the first source/drain region and extending continuously to the second fin in the second source/drain region;
- and
- a second semiconductor layer disposed directly on the first semiconductor layer in the first source/drain region and directly on the first semiconductor layer in the second source/drain region.
A device comprising:
- a first fin disposed over a semiconductor substrate and formed of a first semiconductor layer and a second semiconductor layer, the first fin defining a first channel region and a first source/drain region;
- a second fin disposed over the semiconductor substrate and formed of the first semiconductor layer and the second semiconductor layer, the second fin defining a second channel region and a second source/drain region;
- a gate structure disposed over the first channel region of the first fin and the second channel region of the second fin;
- a third semiconductor layer disposed directly on the first fin in the first source/drain region and extending continuously to the second fin in the second source/drain region;
- and
- a fourth semiconductor layer disposed directly on the third semiconductor layer in the first source/drain region and directly on the third semiconductor layer in the second source/drain region.
Dependencies are inferred from the claim text.