Semiconductor memory device having pads

A semiconductor system, comprising:

• a first area including a first unit, a second unit and a third unit interposed between the first unit and the second unit;
• a second area including a plurality of first interfaces and arranged at one side of the first area;
• and
• a third area including a plurality of second interfaces and arranged at the other side of the first area,
• wherein the first unit receives a first level signal and the second unit receives a second level signal being opposite to the first level signal.

A semiconductor system, comprising:

• a first power pad receiving a first power voltage;
• a pair of second power pads receiving a second power voltage, respectively;
• a first data pad receiving a first data signal and arranged between the first power pad and one of the second power pads;
• and
• a second data pad receiving a second data signal being opposite to the first data signal and arranged between the first power pad and the other of the second power pads.