Power overlay structure having wirebonds and method of manufacturing same

A method of manufacturing a power overlay (POL) structure comprising:

• providing a wafer comprising a plurality of semiconductor devices;
• coupling a dielectric layer to an upper surface of the each of the plurality of semiconductor devices;
• forming a plurality of vias through the dielectric layer to expose at least one contact pad of the plurality of semiconductor devices;
• forming a metallization layer on an upper surface of the dielectric layer, the metallization layer having metal interconnects that extend through the plurality of vias and electrically couple with the at least one contact pad of the plurality of semiconductor devices;
• and
• coupling at least one wirebond to a top surface of the metallization layer.

A power overlay (POL) assembly comprising:

• a first semiconductor device and a second semiconductor device;
• a POL interconnect assembly comprising:
• a polyimide film adhesively coupled to upper contact pads of the first and second semiconductor devices;
• and
• a metallization path formed on the polyimide film, the metallization path comprising a plurality of metal interconnects extending through vias formed through the polyimide film and electrically coupled to the upper contact pads of the first and second semiconductor devices;
• and
• a plurality of copper wirebonds directly coupled to the metallization path;
• wherein a first wirebond of the plurality of copper wirebonds is electrically coupled to an upper contact pad of the first semiconductor device;
• and
• wherein a second wirebond of the plurality of copper wirebonds is electrically coupled to an upper contact pad of the second semiconductor device.