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US 2016/0104659 A1Published application
Stacked Semiconductor Package and Manufacturing Method Thereof
AssigneeAmkor Technology, Inc.
InventorsDong Joo Park, Jae Sung Park, Jin Seong Kim, Ju Hoon Yoon
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Abstract
A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.
Claims20
A stacked semiconductor package, comprising:
- a lower semiconductor package, comprising:
- a substrate;
- a semiconductor chip attached to a center region of an upper surface of the substrate;
- a plurality of terminals attached to and extending upward from a peripheral region of the upper surface of the substrate around the center region;
- and
- a molding compound covering the upper surface of the substrate, at least a portion of side surfaces of the semiconductor chip, and at least a portion of a side surface of each of the terminals,
- wherein at least an upper surface of each of the terminals is exposed from the molding compound;
- and
- an interposer comprising a plurality of contacts on a lower surface;
- and
- an adhesive member bonding the lower surface of the interposer to an upper surface of the lower semiconductor package, wherein the adhesive member comprises conductive particles that conductively couple each of the terminals of the lower semiconductor package and a respective one of the interposer contacts.
8 more elements
A stacked semiconductor package, comprising:
- a lower semiconductor package, comprising:
- a substrate;
- a semiconductor chip attached to a center region of an upper surface of the substrate;
- a plurality of terminals attached to and extending upward from a peripheral portion of the upper surface of the substrate around the center region;
- and
- a molding compound covering the upper surface of the substrate, at least a portion of side surfaces of the semiconductor chip, and at least a portion of a side surface of each of the terminals,
- wherein at least an upper surface of each of the terminals is exposed from the molding compound;
- an upper semiconductor package comprising a plurality of contacts on a lower surface;
- an adhesive member bonding the lower surface of the upper semiconductor package to an upper surface of the lower semiconductor package, wherein the adhesive member comprises conductive particles that conductively couple each of the terminals of the lower semiconductor package and a respective one of the upper semiconductor package contacts.
6 more elements
A stacked semiconductor package, comprising:
- a lower semiconductor package, comprising an interconnection structure exposed from an encapsulating material on an upper surface;
- an interposer comprising an interconnection structure on a lower surface;
- and
- an adhesive member bonding the lower surface of the interposer to an upper surface of the lower semiconductor package, wherein the adhesive member comprises conductive particles that conductively couple the interconnection structure of the lower semiconductor package and the interconnection structure of the interposer.
1 more element
Dependencies are inferred from the claim text.