Self-aligned Double Patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Sheng Chang, Chung-Ju Lee, Tien-I Bao
Life of this patent
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Abstract
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a first patterned mask layer, the first patterned mask layer having a first opening and a second opening, the first opening and the second opening being co-linear, a first end of the first opening having a first center region and first side regions on opposing sides of the first center region, the first side regions extending away from the first center region toward the second opening;
- performing an enlargement process to reduce a distance the first side regions extend from the first center region, thereby forming an enlarged pattern;
- and
- after the performing the enlargement process, transferring the enlarged pattern to an underlying layer, thereby forming openings in the underlying layer.
A method of manufacturing a semiconductor device, the method comprising:
- forming a first line pattern;
- cutting the first line pattern to form a second line pattern and a third line pattern, the second line pattern and the third line pattern, the second line pattern and the third line pattern having concave ends;
- forming a first mask layer along sidewalls of the second line pattern and the third line pattern, wherein the second line pattern and the third line pattern are exposed;
- removing the second line pattern and the third line pattern, thereby forming a first line opening and a second line opening, the first line opening and the second line opening having concave ends corresponding to the concave ends of the second line pattern and the third line pattern;
- and
- enlarging the first line opening and the second line opening, the enlarging reducing a curvature of the concave ends of the first line opening and the second line opening.
A method of manufacturing a semiconductor device, the method comprising:
- forming a dielectric layer over a substrate;
- forming a first masking layer over the dielectric layer;
- forming a second masking layer over the first masking layer, the second masking layer having a first opening and a second opening, the first opening and the second opening having concave ends;
- performing a first process to reduce a curvature of the concave ends;
- etching the first masking layer using the second masking layer as a first mask;
- etching the dielectric layer using the first masking layer as a second mask, thereby forming a third opening and a fourth opening in the dielectric layer;
- and
- filling the third opening and the fourth opening in the dielectric layer with a conductive material.
Dependencies are inferred from the claim text.