Repair circuit and semiconductor memory device including the same

A semiconductor memory device comprising:

• a memory cell array including normal column lines and redundancy column lines;
• a normal decoder suitable for decoding input addresses, and accessing the normal column lines by retaining a predetermined bit of the input addresses in a don't care state in response to a first control signal;
• a comparison unit suitable for comparing the input addresses and repair addresses, and generating a column repair signal for accessing a redundancy column line, among the redundancy column lines;
• and
• a duplication control unit suitable for generating a cut-off signal for cutting off access to the normal column lines, when the column repair signal is activated,
• wherein, in response to a second control signal, the comparison unit excludes predetermined bits of the input addresses and the repair addresses from comparison targets, and the duplication control unit holds the cut-off signal to a predetermined level.

A method for operating a semiconductor memory device including normal column lines and redundancy column lines, comprising:

• comparing input addresses and repair addresses, and wherein remaining bits of the input addresses and the repair addresses, excluding predetermined bits thereof, are compared in a write operation under a double test mode;
• accessing a redundancy column line if the input addresses and the repair addresses correspond to each other as a comparison result of the comparing;
• and
• accessing a first normal column line corresponding to the input addresses based on the comparison result, wherein the first normal column line and a second normal column line, corresponding to the remaining bits of the input addresses but different from the first normal column line in predetermined bits thereof, are accessed in the write operation under the double test mode, regardless of the comparison result.