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US 2016/0104542 A1Published application
Memory cell capable of operating under low voltage conditions
AssigneeeMemory Technology Inc.
InventorsMeng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
Life of this patent
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Abstract
A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.
Claims24
A memory cell comprising:
- a programming selection transistor having a first terminal, a second terminal configured to receive a bit line program signal, and a control terminal configured to receive a word line program signal;
- a following gate transistor having a first terminal, a second terminal coupled to the first terminal of the programming selection transistor, and a control terminal configured to receive a following control signal;
- an antifuse element having a first terminal configured to receive an antifuse control signal, and a second terminal coupled to the first terminal of the following gate transistor;
- and
- a reading circuit coupled to the second terminal of the following gate transistor and configured to form a read current according to a bit line read signal and a selection signal during a reading operation of the memory cell.
2 more elements
A memory array comprising:
- a first memory cell comprising:
- a first programming selection transistor having a first terminal, a second terminal configured to receive a first bit line program signal, and a control terminal configured to receive a first word line program signal;
- a first following gate transistor having a first terminal, a second terminal coupled to the first terminal of the first programming selection transistor, and a control terminal configured to receive a first following control signal;
- a first antifuse element having a first terminal configured to receive a first antifuse control signal, and a second terminal coupled to the first terminal of the first following gate transistor;
- and
- a first reading circuit coupled to the second terminal of the first following gate transistor and configured to form a first read current according to a first bit line read signal and a first selection signal during a reading operation of the first memory cell;
- and
- a second memory cell comprising:
- a second programming selection transistor having a first terminal, a second terminal configured to receive a second bit line program signal, and a control terminal coupled to the control terminal of the first programming selection transistor;
- a second following gate transistor having a first terminal, a second terminal coupled to the first terminal of the second programming selection transistor, and a control terminal coupled to the control terminal of the first following gate transistor;
- a second antifuse element having a first terminal coupled to the first terminal of the first antifuse element, and a second terminal coupled to the first terminal of the second following gate transistor;
- and
- a second reading circuit coupled to the second terminal of the second following gate transistor and configured to form a second read current according to a second bit line read signal and a second selection signal during a reading operation of the second memory cell.
10 more elements
Dependencies are inferred from the claim text.