Semiconductor device
AssigneeSK hynix Inc.
InventorJae Wook YANG
Life of this patent
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Abstract
The semiconductor device may include a memory block including a memory string electrically coupled between a bit line and a common source line, the memory string including source select transistors and memory cells configured to operate in response to operating voltages applied to select lines and word lines coupled to the memory cells and the source select transistors. The semiconductor device may include an operation circuit configured to apply a source voltage to the common source line for an erase operation, and to control floating states of the select lines and the word lines. The operation circuit may be configured to set the select lines to a floating state after the source voltage starts to increase from a precharge level to an erase level.
Claims18
A semiconductor device comprising:
- a memory block including a memory string electrically coupled between a bit line and a common source line, the memory string including source select transistors and memory cells configured to operate in response to operating voltages applied to select lines and word lines coupled to the memory cells and the source select transistors;
- and
- an operation circuit configured to apply a source voltage to the common source line for an erase operation, and to control floating states of the select lines and the word lines,
- wherein the operation circuit is configured to set the select lines to a floating state after the source voltage starts to increase from a precharge level to an erase level.
A computing system including a central processing unit, an interface, and a memory system coupled with one another through a bus,
- wherein the memory system includes a memory controller coupled to a flash memory, the flash memory comprising:
- a memory string electrically coupled between a bit line and a common source line, the memory string including source select transistors and memory cells configured to operate in response to operating voltages applied to select lines and word lines coupled to the memory cells and the source select transistors;
- and
- an operation circuit configured to apply a source voltage to the common source line for an erase operation, and to control floating states of the select lines and the word lines,
- wherein the operation circuit is configured to set the select lines to a floating state after the source voltage starts to increase from a precharge level to an erase level.
Dependencies are inferred from the claim text.