US 2016/0104537 A1Published application

Memory array with memory cells arranged in pages

AssigneeeMemory Technology Inc.

InventorsWei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang

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Abstract

A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.

Claims15

Dependent claims

A memory array, comprising:

a first memory page, comprising:
a first word line configured to receive a first word line signal;
a first select gate line configured to receive a first select gate signal;
a first control line configured to receive a first control line signal;
a first erase line configured to receive a first erase line signal;
and
a plurality of first memory cells each comprising:
a word line node coupled to the first word line;
a select gate coupled to the first select gate line;
a control node coupled to the first control line;
an erase node coupled to the first erase line;
a bit line node configured to receive a bit line signal;
and
a source line node configured to receive a source line signal;
wherein:
bit line nodes of the plurality of first memory cells are configured to receive different bit line signals;
source line nodes of the plurality of first memory cells are configured to receive different source line signals;
and
during an program operation of a selected first memory cell of the plurality of first memory cells, a bit line signal received by the selected first memory cell and a bit line signal received by an unselected first memory cell are at different voltages, and a source line signal received by the selected first memory cell and a source line signal received by the unselected first memory cell are at different voltages.

16 more elements

A memory array, comprising:

a first memory page, comprising:
a first word line configured to receive a first word line signal;
a first select gate line configured to receive a first select gate signal;
a first control line configured to receive a first control line signal;
a first erase line configured to receive a first erase line signal;
and
a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and configured to receive a bit line signal and a source line signal;
and
a second memory page, comprising:
a second control line configured to receive a second control line signal;
a second erase line configured to receive a second erase line signal;
and
a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and configured to receive a bit line signal and a source line signal.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/881,177Filed 13 Oct 2015
Priority: 14 Oct 2014
Published: 14 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…