Nonvolatile memory having memory array with differential cells

A nonvolatile memory, comprising:

• a memory array connected to m word lines and (2+y+n) bit line pairs, wherein the (2+y+n) bit line pairs comprise an erase bit line pair, a program bit line pair, y monitoring bit line pairs and n data bit line pairs,
• wherein each of the word lines is connected with (2+y+n) differential cells of a corresponding row of the memory array, wherein the (2+y+n) differential cells comprise an erase flag differential cell, a program flag differential cell, y monitoring differential cells and n data differential cells, wherein the erase flag differential cell is connected with the erase bit line pair, the program flag differential cell is connected with the program line pair, the y monitoring differential cells are connected with the corresponding monitoring bit line pairs, and the n data differential cells are connected with the corresponding data line pairs,
• wherein the n data differential cells of the row are determined as erased cells or programmed cells according to setting conditions of the erase flag differential cell and the program flag differential cell of the row.