Non-volatile memory cell structure and non-volatile memory apparatus using the same

A non-volatile memory apparatus, comprising:

• a plurality of source lines;
• a plurality of bit lines;
• a plurality of word lines;
• and
• a plurality of non-volatile memory cell structures, arranged in an array, wherein, each of the non-volatile memory cell structures comprises:
• a substrate;
• a first well, disposed on the substrate;
• a second well, disposed on the substrate;
• a third well, disposed on the substrate;
• at least one first transistor, forming on the first well and having a first end coupled to corresponding source line;
• a second transistor, forming on the second well, and having a first end coupled to a second end of the first transistor;
• and
• a third transistor, forming on the third well, and having a first end coupled to a second end of the second transistor, a second end coupled to corresponding bit line,
• wherein, a control end of the first transistor is floated, a control end of the second transistor receives a bias voltage, and a control end of the third transistor is coupled to corresponding word line or a Y-decoding signal, wherein, the third well and the second cell are in same type, and the type of the first well is complementary to a type of the third well.