Apparatuses and methods using dummy cells programmed to different states
AssigneeMicron Technology, Inc.
InventorsTORU TANZAWA, Aaron Yip
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.
Claims25
An apparatus, comprising:
- a first memory string including first and second dummy memory cells;
- a second memory string including first and second dummy memory cells;
- a data line coupled to the first memory string and the second memory string;
- and
- a control unit configured to provide during a memory access operation first and second control signals to activate the first and second dummy memory cells of one of the first and second memory strings and to further deactivate the first or second dummy memory cell of the other one of the first and second memory strings.
An apparatus, comprising:
- a first memory string including a first plurality of dummy memory cells;
- a second memory string including a second plurality of dummy memory cells;
- a data line coupled to the first and second memory strings;
- and
- a control unit configured to provide control signals to the plurality of dummy memory cells to activate all the dummy memory cells of the first plurality of dummy memory cells and to activate a first dummy memory cell of the second plurality of dummy memory cells and deactivate a second dummy memory cell of the second plurality of dummy memory cells.
An apparatus, comprising:
- a source;
- a first memory string including a first plurality of memory cells and a first plurality of dummy memory cells, wherein the first memory string is coupled to the source through a first source select gate;
- a second memory string including a second plurality of memory cells and a second plurality of dummy memory cells, wherein the second memory string is coupled to the source through a second source select gate;
- a data line coupled to the first and second memory strings;
- and
- a control unit configured to provide control signals during a memory operation to the plurality of dummy memory cells and to the first and second source select gates to couple the first plurality of memory cells to the source and to further decouple the second plurality of memory cells from the source by deactivating a dummy memory cell of the second plurality of dummy memory cells.
A method, comprising:
- programming a first set of dummy cells associated with a first dummy word line to a first state, wherein the first dummy word line is associated with a plurality of strings in a memory block;
- programming a second set of dummy cells associated with the first dummy word line to a second state;
- programming a third set of dummy cells associated with a second dummy word line to the first state, wherein the second dummy word line is associated with the plurality of strings in the memory block;
- programming a fourth set of dummy cells associated with the second dummy word line to the second state;
- and
- providing a voltage to the first dummy word lines during a memory access operation sufficient to activate the first set of dummy cells and deactivate the second set of dummy cells.
Dependencies are inferred from the claim text.