Content addressable memory cells, memory arrays and methods of forming the same
AssigneeSanDisk 3D LLC
InventorChristopher J. Petti
Life of this patent
Estimating the term…
Abstract
A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.
Claims22
A content addressable memory cell comprising:
- a plurality of transistors comprising a minimum feature size F;
- and
- a plurality of memory elements coupled to the plurality of transistors,
- wherein the content addressable memory cell comprises an area of between 18F2 and 36F2.
A content addressable memory cell comprising:
- five vertically-oriented pillar-shaped transistors;
- and
- two reversible resistance-switching memory elements coupled to the five vertically-oriented pillar-shaped transistors.
A content addressable memory cell for use with a bit line, a complementary bit line, a word select line, a read/write line, a search line, a complementary search line, and a match line, the content addressable memory cell comprising:
- a first transistor comprising a first terminal coupled to the bit line, a second terminal coupled to the word select line, and a third terminal;
- a first reversible resistance-switching element comprising a first terminal coupled to the third terminal of the first transistor, and a second terminal coupled to the read/write line;
- a second transistor comprising a first terminal coupled to the complementary bit line, a second terminal coupled to the word select line, and a third terminal;
- a second reversible resistance-switching element comprising a first terminal coupled to the third terminal of the second transistor, and a second terminal coupled to the read/write line;
- a third transistor comprising a first terminal coupled to the search line, a second terminal coupled to the first terminal of the first reversible resistance-switching element and the third terminal of the first transistor, and a third terminal;
- a fourth transistor comprising a first terminal coupled to the complementary search line, a second terminal coupled to the first terminal of the second reversible resistance-switching element and the third terminal of the second transistor, and a third terminal;
- and
- a fifth transistor comprising a first terminal coupled to the match line, a second terminal coupled to the third terminal of the third transistor and the third terminal of the fourth transistor, and a third terminal coupled to GROUND.
A method of forming a content addressable memory cell, the method comprising:
- providing a plurality of transistors comprising a minimum feature size F;
- and
- providing a plurality of memory elements coupled to the plurality of transistors,
- wherein the content addressable memory cell comprises an area of between 18F2 and 36F2.
Dependencies are inferred from the claim text.