Method of writing memory with regulated ground nodes
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
Estimating the term…
A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
A method of writing data to an accessed memory cell of an accessed column of an accessed section of an accessed segment of a memory array of memory cells;
A method of writing data to a memory array of memory cells, the memory array comprising a plurality of segments, each segment of the plurality of segments comprising a plurality of columns of memory cells, each column of the plurality of columns of memory cells comprising a column internal ground node, a first switch between the column internal ground node and a first voltage node, a second switch between the column internal ground node and a second voltage node, and a third switch between the column internal ground node and a third voltage node, and the method comprising:
The method of claim 11, further comprising:
A method of writing data to a memory array of memory cells, the memory array comprising a plurality of segments, each segment of the plurality of segments comprising a plurality of columns of memory cells, each column of the plurality of columns of memory cells comprising a column internal ground node, a first switch between the column internal ground node and a first voltage node, a second switch between the column internal ground node and a second voltage node, and a third switch between the column internal ground node and a third voltage node, and the method comprising:
Dependencies are inferred from the claim text.