US 2016/0104524 A1Published application

Integrated circuit

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorJhon Jhy LIAW

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Abstract

An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration.

Claims20

Dependent claims

An integrated circuit comprising:

a plurality of first memory cells, each cell of the plurality of first memory cells comprising:
a first inverter;
a second inverter, each inverter of the first and second inverters comprising:
a P-type single FinFET (first PU) transistor;
and
an N-type single FinFET (first PD) transistor;
a first pass-gate (PG) transistor;
and
a second PG transistor, the first PG transistor and the second PG transistor each being an N-type single FinFET transistor;
wherein a first X-pitch (X1) of each cell of the plurality of first memory cells extends in a first direction;
and
a plurality of second memory cells, each cell of the plurality of second memory cells comprising:
a third inverter;
a fourth inverter, each inverter of the third and fourth inverters comprising:
a P-type single FinFET (second PU) transistor, and
an N-type (second PD) transistor comprising at least two FinFET transistors electrically coupled in a parallel configuration;
a third PG transistor, and
a fourth PG transistor, each transistor of the third PG transistor and the fourth PG transistor including at least two FinFET transistors electrically coupled in a parallel configuration;
and
wherein a second X-pitch (X2) of each cell of the plurality of second memory cells extends in the first direction, and X2 being greater than X1.

17 more elements

An integrated circuit comprising:

a plurality of first synchronous random access memory (SRAM) cells, each cell of the plurality of first SRAM cells comprising:
a first inverter;
a second inverter, each inverter of the first and second inverters comprises:
a P-type single FinFET transistor (first PU);
and
an N-type single FinFET transistor (first PD);
a first pass-gate (PG) transistor;
and
a second PG transistor, the first PG transistor and the second PG transistor each being an N-type single FinFET transistor;
wherein a first X-pitch (X1) of each cell of the plurality of first SRAM cells extends in a first direction, and
a plurality of second SRAM cells, each cell of the plurality of second SRAM cells comprises:
a third inverter;
a fourth inverter, each inverter of the third and fourth inverters comprising:
a P-type single FinFET transistor (second PU), and
an N-type (second PD) transistor comprising at least two FinFET transistors electrically coupled in a parallel configuration;
a third PG transistor, and
a fourth PG transistor, each transistor of the third PG transistor and the fourth PG transistor comprising at least two FinFET transistors electrically coupled in a parallel configuration;
wherein a second X-pitch (X2) of each cell of the plurality of second SRAM cells extends in the first direction;
a first data line;
a second data line;
a third data line;
and
a fourth data line;
wherein
each cell of the plurality of first SRAM cells is coupled to a write assist circuit, the write assist circuit being configured to assist a write cycle capability of each cell of the plurality of first SRAM cells;
the write assist circuit comprising a negative voltage generator coupled to the first data line and the second data line of each cell of the plurality of first SRAM cells;
during a write cycle of a first cell of the plurality of first SRAM cells, the first data line, coupled to the first cell of the plurality of first SRAM cells, is discharged to a low voltage state, and the second data line, coupled to the first cell of the plurality of first SRAM cells, is pre-charged to a high voltage state;
and
the negative voltage generator is configured to reduce a voltage of the first data line, coupled to the first cell of the plurality of first SRAM cells, being lower than the low voltage state, if the negative voltage generator is enabled.

26 more elements

An integrated circuit, comprising:

a plurality of first synchronous random access memory (SRAM) cells, each cell of the plurality of first SRAM cells comprising:
a first inverter;
a second inverter;
each inverter of the first and second inverters comprising:
a P-type single FinFET (first PU) transistor;
and
an N-type single FinFET (first PD) transistor;
a first pass-gate (PG) transistor;
and
a second PG transistor, each PG transistor of the first and second PG transistors is an N-type single FinFET transistor;
a plurality of second SRAM cells, each cell of the plurality of second SRAM cells comprising:
a third inverter;
a fourth inverter, each inverter of the third and fourth inverters comprising:
a P-type single FinFET (second PU) transistor, and
an N-type (second PD) transistor including at least two FinFET transistors electrically coupled in a parallel configuration;
a third PG transistor, and
a fourth PG transistor, each of the third PG transistor and the fourth PG transistor comprising at least two FinFET transistors electrically coupled in a parallel configuration;
a first power line coupled to a first power supply and each cell of the plurality of first SRAM cells;
a second power line coupled to a second power supply and each cell of the plurality of second SRAM cells, the first power supply being configured to provide a voltage different than the second power supply;
wherein
a first X-pitch (X1) of each cell of the plurality of first memory cells extends in a first direction;
and
a second X-pitch (X2) of each cell of the plurality of second memory cells extends in the first direction, and X2 is greater than X1.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/970,619Filed 16 Dec 2015
Priority: 20 Jun 2014
Published: 14 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
G11C
Static stores

Family

Application14/310,399Continuation · filed 20 Jun 2014
Application14/970,619Continuation
US 10,381,070 B2Related patent
US 2015/0371701 A1Published application
US 9,218,872 B1Related patent
US 2016/0104524 A1This patent

From the US filing history. Foreign family members aren’t listed.