Static random access memory and method thereof
AssigneeM31 Technology Corporation
InventorNan-Chun Lien
Life of this patent
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Abstract
A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.
Claims18
A static random access memory (SRAM), comprising:
- a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, wherein the first power supply voltage has a substantially same voltage as the positive power supply voltage during a first period of a write operation, and the first power supply voltage has a reduced level that is lower than the positive power supply voltage and is higher than a retention voltage during a second period of the same write operation subsequent to the first period;
- a first inverter connected between the first power supply voltage and a second power supply voltage;
- and
- a second inverter connected between the first power supply voltage and the second power supply voltage;
- wherein the first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.
A method of operating a static random access memory (SRAM), comprising:
- asserting a word line;
- discharging one node of a bit node pair of the SRAM through one line of a bit line pair;
- generating a first power supply voltage for the SRAM with a substantially same voltage as a positive power supply voltage during a first period of a write operation, and with a reduced level that is less than the positive power supply voltage during a second period of the same write operation subsequent to the first period;
- and
- inducing a negative bit line voltage on the one line of the bit line pair owing to a parasitic couple capacitance between a line of the first power supply voltage and the one line of the bit line pair.
Dependencies are inferred from the claim text.