Clock signal processor and non-volatile memory device including the same

A non-volatile memory device comprising:

• a memory cell array;
• a control circuit configured to generate a row address signal and a column address signal based on a command signal and an address signal, the control circuit including a clock signal processor configured to generate a data strobe signal based on a second read clock signal, which is changed from a first read clock signal during a read operation;
• an address decoder configured to activate a word line corresponding to the row address signal;
• and
• a data I/O circuit configured to receive read data of memory cells connected to the word line through a plurality of bit lines based on the column address signal, and configured to output the read data as a data signal;
• the clock signal processor including
• a duty cycle corrector configured to generate a third read clock signal by modifying a duty cycle of the second read clock signal,
• a switch point calculator configured to activate a switch signal at an end of a latency period in which a read command is provided as the command signal and an invalid data is read from the non-volatile memory device, and
• a multiplexer configured to output one of the second and third read clock signals as the data strobe signal based on the switch signal.

A method of processing a clock signal comprising:

• outputting an input clock signal of a non-volatile memory device as an output clock signal;
• generating a modified input clock signal by modifying a duty cycle of the input clock signal during a latency period in which a read command is provided to the non-volatile memory device and an invalid data is read from the non-volatile memory device;
• and
• outputting the modified input clock signal as the output clock signal from an end of the latency period.