High temperature data retention in magnetoresistive random access memory

A method for storing data in a magnetoresistive memory device, comprising:

• selecting a first magnetic memory cell in an array of magnetic memory cells, wherein each magnetic memory cell in the array includes a magnetic tunnel junction that includes a dielectric layer;
• after selecting the first magnetic memory cell, applying a breakdown voltage to the first magnetic memory cell, wherein the breakdown voltage has sufficient magnitude to break down the dielectric layer in the magnetic tunnel junction included in the magnetic memory cell, wherein applying the breakdown voltage further comprises at least one of:
• exposing the magnetoresistive memory device to an external magnetic field that makes the dielectric layer in the magnetic tunnel junction of the first magnetic memory cell more susceptible to breakdown;
• exposing the magnetoresistive memory device to a heat source to elevate temperature of the first magnetic memory cell above a normal operating temperature range;
• and
• generating the breakdown voltage using a voltage greater than voltages used during normal operation of the magnetoresistive memory device;
• determining that a second magnetic memory cell in the array of magnetic memory cells has normal-resistance magnetic tunnel junction, wherein the normal-resistance magnetic tunnel junction indicates that the second magnetic memory cells stores a first data value;
• and
• after applying the breakdown voltage, determining that the first magnetic memory cell has a magnetic tunnel junction with a broken-down dielectric layer, wherein the broken-down dielectric layer indicates that the first magnetic memory cell stores a second data value that is different than the first data value.

A magnetoresistive memory device, comprising:

• a first plurality of magnetic memory cells configured to store data;
• a first plurality of select transistors, wherein each of the first plurality of select transistors is coupled to a corresponding magnetic memory cell of the first plurality of magnetic memory cells;
• a second plurality of magnetic memory cells, wherein the second plurality of magnetic memory cells includes:
• intact magnetic memory cells having a normal-resistance magnetic tunnel junction;
• and
• broken-down magnetic memory cells having a magnetic tunnel junction that includes a dielectric layer that has broken down such that the broken-down magnetic memory cells have a resistance substantially lower than a resistance of the intact magnetic memory cells;
• circuitry coupled to the second plurality of memory cells, the circuitry capable of conducting a breakdown current through selected magnetic memory cells of the second plurality of magnetic memory cells, wherein the breakdown current results in a breakdown voltage that breaks down the dielectric layer included in magnetic tunnel junctions of intact magnetic memory cells, wherein the circuitry includes at least one of:
• oversized select transistors coupled to the second plurality of memory cells, wherein the oversized select transistors are capable of carrying more current than select transistors included in the first plurality of select transistors;
• and
• circuitry for coupling a set of select transistors in parallel in order to allow a portion of the breakdown current to be sent through each select transistor in the set;
• and
• read circuitry coupled to the first and second pluralities of magnetic memory cells.