Memory Device With Timing Overlap Mode
AssigneeEverspin Technologies, Inc.
InventorsThomas Andre, Syed M. Alam, Halbert S. Lin
Life of this patent
Estimating the term…
Abstract
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
Claims21
1-20. (canceled)
A memory device comprising:
- a circuit to receive a first command to cause the circuit to perform a first operation and a second command to cause the circuit to perform a second operation;
- wherein the first operation and the second operation are completed by the circuit prior to an expiration of a period of time, the period of time representing a number of clock cycles that an external source waits after providing the first command plus a number of clock cycles the external source waits after providing the second command.
The memory device as recited in claim 1, wherein the circuit includes:
- a precharge timing circuit to perform the first operation;
- and
- an activate timing circuit to perform the second operation.
The memory device as recited in claim 1, wherein the circuit includes an overlap circuit to delay an initiation of the second operation until a completion of the first operation.
The memory device as recited in claim 1, wherein:
- the number of clock cycles that the external source waits after providing the first command is a period associated with a row-precharge-time;
- and
- the number of clock cycles that the external source waits after providing the second command is a period associated with a row-address-to-column-address delay.
The memory device as recited in claim 1, wherein the period of time elapses prior to the circuit receiving a third command.
The memory device as recited in claim 1, wherein the first operation is related to writing content of a cache associated with the memory device into a memory bank of the memory device.
The memory device as recited in claim 1, wherein the second operation is related to writing content of a memory bank of the memory device into a cache associated with the memory device.
A system comprising:
- a circuit to generate a first command and a second command, the first command and the second command associated with accessing data;
- and
- a memory device to store the data, the memory device to, at least in part in response to receiving the first command, initiate a first operation associated with the first command and to temporarily prevent an initiation of a second operation associated the second command.
The system as recited in claim 8, further comprising a cache accessible to the circuit and to the memory device.
The system as recited in claim 9, wherein the first operation and the second operation are associated with accessing data via the cache.
The system as recited in claim 8, wherein the first command is a precharge command and the second command is an activate command.
The system as recited in claim 8, wherein the memory device initiates the second operation at least in part in response to a completion of the first operation.
The system as recited in claim 8, further comprising an enable circuit coupled to the memory device, the enable circuit to generate an override signal to cause the memory device to initiate the second operation prior to the completion of the first operation.
The system as recited in claim 8, wherein the circuit is an external source.
A method comprising:
- receiving, at a circuit, a command from an external source, the command associated with accessing a data store in a memory device;
- generating, by the circuit, a control signal to at least in part initiate a series of events related to the command;
- receiving, at the circuit, an additional command;
- receiving, at the circuit, a signal indicating a completion of the series of events related to the command;
- and
- generating, by the circuit, an additional control signal to at least in part initiate an additional series of events related to the additional command.
The method as recited in claim 15, wherein the command is a precharge command and the additional command is an activate command.
The method as recited in claim 15, wherein the generating of the additional control signal is at least in part in response to the receiving of the signal indicating the completion of the series of events related to the command.
The method as recited in claim 15, further comprising:
- providing the control signal to a second circuit, the second circuit to perform the series of events related to the command;
- and
- providing the additional control signal to a third circuit, the third circuit to perform the additional series of events related to the additional command.
The method as recited in claim 15, further comprising:
- providing the control signal to a second circuit, the second circuit to perform the series of events related to the command;
- and
- providing the additional control signal to the second circuit, the second circuit to perform the additional series of events related to the additional command.
The method as recited in claim 15, further comprising:
- receiving, at the circuit, an override signal;
- and
- wherein the generating of the additional control signal is at least in part in response to receiving the override signal.
Dependencies are inferred from the claim text.