Semiconductor storage device
AssigneeRenesas Electronics Corporation
InventorsTetsuo FUKUSHI, Atsunori HIROBE, Toshikatsu JINBO, Muneaki MATSUSHIGE
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Abstract
A semiconductor storage device 1 according to an aspect includes a first memory area 11_1 and a second memory area 11_2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm_ are disposed in a boundary area 18 between the first and second memory areas 11_1 and 11_2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
Claims5
A semiconductor storage device, comprising:
- a first and a second memory region, each of the first and second memory region including a plurality of memory cell array units;
- a first memory cell array unit in the first memory region having a plurality of first sense amplifiers, a plurality of first bit line pairs extending both sides of the first sense amplifiers, and a plurality of first memory cells connected to the first bit line pairs;
- a second memory cell array unit in the second memory region having a plurality of second sense amplifiers, a plurality of second bit line pairs extending both sides of the second sense amplifiers, and a plurality of second memory cells connected to the second bit line pairs;
- a first power supply line arranged to surround the first and second memory region;
- a second power supply line extending in a word-line direction and being connected to the first power supply line;
- wherein one of the first bit line pairs and one of the second bit line pairs are alternately provided in the word-line direction between the first and second sense amplifiers,
- wherein first word lines connected to the first memory cells and the second memory cells between the first and second sense amplifiers are in an inactivate state, and
- wherein the second power supply line is formed between the first and second sense amplifiers so as to overlap the first and second memory cells between the first and second sense amplifiers in plane view.
Dependencies are inferred from the claim text.