Decryption of encrypted instructions using keys selected on basis of instruction fetch address

A method of securely executing encrypted instructions within a microprocessor, the method comprising:

• storing a plurality of master keys in a secure memory;
• fetching encrypted instructions from an instruction cache;
• selecting a set of one or more master keys from the secure memory based upon an encrypted instruction fetch address;
• decrypting an encrypted instruction fetched from the instruction cache using the selected set of one or more master keys or a decryption key derived from the selected set of one or more master keys to decrypt the encrypted instructions fetched from the instruction cache;
• and
• securely executing the decrypted instructions within the microprocessor.

A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

• computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising:
• first program code for specifying an instruction cache operable to store encrypted instructions;
• second program code for specifying fetch logic configured to fetch encrypted instructions from the instruction cache;
• third program code for specifying a secure memory configured to store a plurality of master keys;
• fourth program code for specifying key selection logic configured to select a set of one or more master keys based upon an encrypted instruction fetch address;
• and
• fifth program code for specifying decryption logic configured to use the selected set of one or more master keys or a decryption key derived from the selected set of one or more master keys to decrypt the encrypted instructions fetched from the instruction cache.