Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout

An apparatus comprising:

• at least one processor;
• and
• at least one memory including computer program code for one or more programs, wherein the at least one processor is configured to execute an instruction, based on the computer program code, to cause the apparatus to:
• generate a plurality of multiple patterning decompositions associated with a layout of an integrated circuit, each of the plurality of multiple patterning decompositions comprising:
• a first pattern associated with a first mask;
• a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set;
• a width value associated with at least one of the first pattern or the second pattern;
• and
• a first spacing value between the first pattern and the second pattern;
• generate a file comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions, the plurality of dielectric constant values being based on the width values and the first spacing values associated with the plurality of multiple patterning decompositions;
• generate a first sub-file associated with worst-case performance dielectric constant values based on second spacing values between the first pattern and the second pattern, and a range of width values of all first patterns of the plurality of multiple patterning decompositions;
• and
• generate a second sub-file associated with worst-case performance dielectric constant values based on third spacing values between the second pattern and the first pattern, and a range of width values of all second patterns of the plurality of multiple patterning decompositions.

A non-transitory computer-readable storage medium carrying one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:

• generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit, each of the plurality of multiple patterning decompositions comprising:
• a first pattern associated with a first mask;
• a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set;
• a width value associated with at least one of the first pattern or the second pattern;
• and
• a first spacing value between the first pattern and the second pattern;
• generating a file comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions, the plurality of dielectric constant values being based on the width values and the first spacing values associated with the plurality of multiple patterning decompositions;
• generating a first sub-file associated with nominal dielectric constant values based on second spacing values between at least two separated first patterns, and a range of width values of all first patterns of the plurality of multiple decomposition patterns;
• and
• generating a second sub-file associated with nominal dielectric constant values based on third spacing values between at least two separated second patterns, and a range of width values of all second patterns of the plurality of multiple decomposition patterns.