Method and apparatus for emulation and prototyping with variable cycle speed
AssigneeSynopsys, Inc.
InventorsAlexander Rabinovitch, Cedric Alquier
Life of this patent
Estimating the term…
Abstract
A hardware verification system includes, in part, a multitude of programmable devices and a system clock. The hardware verification system receives a circuit design and generates a variable period clock from the system clock by analyzing propagation delays in different signal paths of the circuit design. The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, in which M>N. The variable period clock is applied to at least one of the programmable devices to verify the circuit design.
Claims26
A hardware verification system comprising a plurality of programmable devices and a system clock, the hardware verification system configured to:
- generate a variable period clock signal from the system clock, the variable period clock signal having a first period and a second period greater than the first period, said first period occurring in each N cycles of the system clock and said second period occurring in each M cycles of the system clock, wherein N and M are integer values greater than zero;
- and
- apply the variable period clock signal to at least a first subset of the plurality of programmable devices.
A method of verifying a design using a plurality of programmable devices and a system clock, the method comprising:
- causing a variable period clock signal to be generated from the system clock when the design is received by the plurality of programmable devices, said variable period clock having a first period and a second period greater than the first period, said first period occurring in each N cycles of the system clock and said second period occurring in each M cycles of the system clock, wherein N and M are integer values greater than zero.
An apparatus for verifying a design using a plurality of programmable devices and a system clock, comprising:
- means for causing a variable period clock signal to be generated from the system clock when the design is received by the plurality of programmable devices, said variable period clock having a first period and a second period greater than the first period, said first period occurring in each N cycles of the system clock and said second period occurring in each M cycles of the system clock, wherein N and M are integer values greater than zero;
- and
- means for applying the variable period clock signal to at least a first one of the plurality of programmable devices to verify the design.
Dependencies are inferred from the claim text.