Unified tool for automatic design constraints generation and verification
AssigneeOracle International Corporation
InventorsYibin XIA, Dinesh Rajasavari AMIRTHARAJ, Ali VAHIDSAFA, Alan SMITH, Senthilkumar DIRAVIAM, Mohd Jamil MOHD
Life of this patent
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Abstract
Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.
Claims20
A computer-implemented method comprising:
- reading, by a unified tool,
- (i) design data for a circuit design, and
- (ii) design intent information for the circuit design;
- and
- generating, by the unified tool,
- (i) physical flow elements of the circuit design, and
- (ii) verification flow elements of the circuit design,
- wherein the generating physical flow elements and the generating verification flow elements are performed together and in dependence on each other by the unified tool based, at least in part, on the design data and the design intent information.
A computing system, comprising:
- model creating logic configured to read data structures comprising design data of a circuit design and generate computerized design models based on the design data;
- domain tagging logic configured to:
- read data structures comprising a design intent specification of the circuit design,
- perform an analysis of the computerized design models using at least clock and power information from the design intent specification, and
- tag the computerized design models with clock domains and power domains identified by the analysis;
- boundary identification logic configured to identify, from the computerized design models, crossings of the clock domains and crossings of the power domains;
- constraint generation logic configured to analyze and cross-check a design intent of the design intent specification with the computerized design models and generate design constraints for a physical flow of the circuit design;
- and
- test bench and assertion generation logic configured to analyze and cross-check the design intent of the design intent specification with the computerized design models and generate test benches and assertions for a verification flow of the circuit design.
A non-transitory computer-readable medium storing computer-executable instructions that, when executed by a processor of a computer, cause the computer to perform a method, wherein the instructions comprise:
- instructions for reading data structures comprising design data for a circuit design, using at least hardware of the computer;
- instructions for building computerized design models of the circuit design based on the design data;
- instructions for reading data structures comprising a design intent specification for the circuit design;
- instructions for analyzing and cross-checking the design intent specification with the computerized design models;
- and
- instructions for generating based, at least in part, on the analyzing and cross-checking:
- (i) design constraints for a physical flow of the circuit design, and
- (ii) test benches and assertions for a verification flow of the circuit design,
- wherein the generating is configured to ensure that the design constraints, the test benches, and the assertions are consistent with each other.
Dependencies are inferred from the claim text.