System for and method of designing an integrated circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWan-Yen LIN, Shu-Yu CHEN, Yu-Ti SU
Life of this patent
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Abstract
A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.
Claims20
A method of designing an integrated circuit, the method comprising:
- receiving a first list corresponding to at least one circuit component in a layout, wherein the at least one circuit component comprises:
- an electrostatic discharge (ESD) circuit, and
- an associated ESD current path;
- generating, by a processor, a condensed layout from the layout, wherein the condensed layout comprises the at least one circuit component;
- and
- performing an ESD check of the condensed layout, wherein the ESD check is configured to verify compliance with one or more ESD design rules.
A system for designing an integrated circuit, comprising:
- at least one processor;
- and
- at least one memory including computer program code for one or more programs, the at least one memory and the computer program code being configured to, with the at least one processor, cause the system to:
- receive a first list corresponding to at least one circuit component in a layout, wherein the at least one circuit component comprises:
- an electrostatic discharge (ESD) circuit;
- an associated ESD current path;
- a layer number on which the ESD circuit is located;
- generate a condensed layout from the layout, wherein the condensed layout comprises the at least one circuit component;
- perform an ESD check of the condensed layout, wherein the ESD check is configured to verify compliance with one or more ESD design rules.
A computer readable medium comprising computer executable instructions for carrying out a method of designing an integrated circuit, the method comprising:
- receiving a first list corresponding to at least one circuit component in a layout, wherein the at least one circuit component comprises:
- an electrostatic discharge (ESD) circuit;
- an associated ESD current path;
- and
- one or more first metal portions directly connected to the ESD circuit or adjacent to the ESD circuit;
- generating a condensed layout from the layout, wherein the condensed layout comprises the at least one circuit component;
- performing an ESD check of the condensed layout, wherein the ESD check is performed to verify compliance with one or more ESD design rules.
Dependencies are inferred from the claim text.