Low latency device interconnect using remote memory access with segmented queues

A computer system comprising:

• a first computing device configured to write messages to message buffers in a circular message queue as indicated by an advancing tail pointer, the circular message queue mapped to remote memory in a second computing device, the message buffers divided into at least two queue segments, each queue segment having two or more message buffers;
• the second computing device configured to read messages from the message buffers of the circular message queue as indicated by an advancing head pointer that indicates a message buffer of one of the queue segments, the second computing device configured to read a message from a next message buffer when determining that the next message buffer has been newly written to since the head pointer last indicated the next message buffer;
• a peer-to-peer data link connecting the second computing device and the first computing device;
• the first computing device configured to advance the tail pointer from one message buffer to another message buffer within a same queue segment after writing a message to the one message buffer, and the first computing device configured to advance the tail pointer from a message buffer of a current queue segment to a message buffer of a next queue segment when determining that the head pointer does not indicate any of the message buffers of the next queue segment.

A computing device comprising:

• memory configured to store a circular message queue of message buffers divided into at least two queue segments, each queue segment having two or more message buffers;
• a high-speed serial expansion bus adapter card;
• and
• a processor coupled to the memory and the high-speed serial expansion bus adapter card, the processor configured to write messages to the message buffers in the circular message queue as indicated by an advancing tail pointer, the processor further configured to replicate the circular message queue to remote memory at a remote computing device via the high-speed serial expansion bus adapter card;
• the processor further configured to advance the tail pointer from one message buffer to another message buffer within a same queue segment after writing a message to the one message buffer;
• the processor further configured to advance the tail pointer from a message buffer of a current queue segment to a message buffer of a next queue segment when determining that a head pointer for reading messages at the remote computing device does not indicate any of the message buffers of the next queue segment.

A computing device comprising:

• memory configured to store a circular message queue of message buffers divided into at least two queue segments, each queue segment having two or more message buffers;
• a high-speed serial expansion bus adapter card;
• and
• a processor coupled to the memory and the high-speed serial expansion bus adapter card, the processor further configured to replicate the circular message queue in the memory as received from a remote computing device via the high-speed serial expansion bus adapter card;
• the processor further configured to read messages from the message buffers of the circular message queue as indicated by an advancing head pointer that indicates a message buffer of one of the queue segments, the processor further configured to read a message from a next message buffer when determining that the next message buffer has been newly written to since the head pointer last indicated the next message buffer;
• the processor further configured to control guard flags of the queue segments, each guard flag indicating to the remote computing device whether writing to a respective queue segment is permitted.