Memory aggregation device

A memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, both the set of input data streams and the set of output data streams being operable to perform one of sending and stop sending new data in each clock cycle, the memory aggregation device comprising:

• a set of first-in first-out (FIFO) memories each comprising an input and an output;
• an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix;
• an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix;
• an input selector configured to select the input interconnection matrix such that data streams of the set of input data streams having valid data requests are compressed to a continuous set of data requests in the set of FIFO memories;
• an output selector configured to select the output interconnection matrix according to an output data scheduling scheme;
• and
• a memory controller coupled to both, the input selector and the output selector.

A method for storing a set of input data streams in a set of first-in first-out (FIFO) memories and retrieving data from the set of FIFO memories to a set of output data streams, both the set of input data streams and the set of output data streams being operable to perform one of sending and stop sending new data in each clock cycle, the method comprising:

• interconnecting each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix;
• interconnecting each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix;
• selecting the input interconnection matrix according to an input data scheduling scheme;
• selecting the output interconnection matrix according to an output data scheduling scheme;
• and
• controlling the input data scheduling scheme such that data from the set of input data streams is spread among the set of FIFO memories in a round-robin manner and controlling the output data scheduling scheme such that data from the set of FIFO memories is retrieved to the set of output data streams in a round-robin manner.