Memory page buffer
AssigneeMacronix International Co., Ltd.
InventorsChung-Kuang Chen, Han-Sung Chen, Chung-Hsiung Hung
Life of this patent
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Abstract
One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.
Claims16
A memory device, comprising:
- a plurality of page buffer circuits, different page buffer circuits in the plurality of page buffer circuits coupled to different bit lines in a plurality of bit lines in a memory array;
- control circuitry responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.
A method, comprising:
- receiving a program command to program multiple memory cells coupled to different bit lines in a memory array;
- responsive to the program command, setting different target voltages at a same time for the different bit lines coupled to the multiple memory cells.
A memory device, comprising:
- a page buffer circuit of a bit line in a memory array, including:
- a plurality of memory elements storing a plurality of bits;
- a plurality of electrical inputs of the page buffer circuit, different ones of the plurality of electrical inputs corresponding to different signals that result in different bit line voltages of the bit line;
- and
- a selection circuit that, based on the plurality of bits in the plurality of memory elements, selects a particular electrical input of the plurality of electrical inputs.
Dependencies are inferred from the claim text.