Methods and apparatus for recovering errors with an inter-processor communication link between independently operable processors
AssigneeApple Inc.
InventorsKaran Sanghi, Saurabh Garg, Haining Zhang
Life of this patent
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AssigneeApple Inc.
InventorsKaran Sanghi, Saurabh Garg, Haining Zhang
Estimating the term…
Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
Processor apparatus adapted for use in a portable device, the processor apparatus comprising:
A method of operating a processor in a multi-processor system or apparatus, the method comprising:
Error-tolerant integrated circuit apparatus, comprising:
Dependencies are inferred from the claim text.